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ISO-CMOS MT8806 8 x 4 Analog Switch Array
Features
* * * * * * * * * * Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 13.2V 12Vpp analog signal capability R ON 65 max. @ V DD=12V, 25C R ON 10 @ V DD=12V, 25C Full CMOS switch for low distortion Minimum feedthrough and crosstalk Separate analog and digital reference supplies Low power consumption ISO-CMOS technology
ISSUE 2
November 1988
Ordering Information MT8806AC 24 Pin Ceramic DIP MT8806AE 24 Pin Plastic DIP MT8806AP 28 Pin PLCC -40 to 85C
Description
The Mitel MT8806 is fabricated in MITEL's ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 4 array of crosspoint switches along with a 5 to 32 line decoder and latch circuits. Any one of the 32 switches can be addressed by selecting the appropriate five address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Chip Select (CS) allows the crosspoint array to be cascaded for matrix expansion.
Applications
* * * * * * Key systems PBX systems Mobile radio Test equipment/instrumentation Analog/digital multiplexers Audio/Video switching
CS
STROBE
DATA RESET
VDD
VEE
VSS
1 AX0
1 ****************
AX1 AY0 AY1 AY2 32 32
8x4 5 to 32 Decoder Latches Switch Array
Xi I/O (i=0-3)
*******************
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
3-9
MT8806
ISO-CMOS
24 PIN CERDIP/PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #* 1-3 4 5 6 7 8 9 10 11 12 13 14-16 17 Name Y2-Y0 DATA X0 AX0 X1 AX1 X2 CS X3 VSS VEE Description Y2-Y0 Analog (Inputs/Outputs): these are connected to the Y2-Y0 columns of the switch array. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. X0 Analog (Input/Output): this is connected to the X0 row of the switch array. X0 Address Line (Input). X1 Analog (Input/Output): this is connected to the X1 row of the switch array. X1 Address Line (Input). X2 Analog (Input/Output): this is connected to the X2 row of the switch array. Chip Select (Input): this is used to select the device. Active High. X3 Analog (Input/Output): this is connected to the X3 row of the switch array. Digital Ground Reference. Negative Power Supply.
AY0-AY2 Y0 -Y2 Address Lines (Inputs). STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. RESET Y7-Y3 VDD Master RESET (Input): this is used to turn off all switches regardless of the condition of CS. Active High. Y7-Y3 Analog (Inputs/Outputs): these are connected to the Y7-Y3 columns of the switch array. Positive Power Supply.
18 19-23 24
* Plastic DIP and CERDIP only
3-10
CS X3 VSS VEE AY0 AY1 NC
Y2 Y1 Y0 DATA X0 AX0 X1 AX1 X2 CS X3 VSS
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD Y3 Y4 Y5 Y6 Y7 RESET STROBE AY2 AY1 AY0 VEE
4 3 2 1 28 27 26
*
NC Y0 Y1 Y2 VDD Y3 Y4
12 13 14 15 16 17 18
NC D0 J0 D1 J1 D2 J2
5 6 7 8 9 10 11
25 24 23 22 21 20 19
Y5 Y6 Y7 RESET STROBE AY2 NC
28 PIN PLCC
ISO-CMOS
Functional Description
The MT8806 is an analog switch matrix with an array size of 8 x 4. The switch array is arranged such that there are 8 columns by 4 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 32 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0 & AX1). Data is presented to the memory on the DATA input. Data is asynchronously written into memory whenever both the CS (Chip Select) and the STROBE inputs are high and is latched on the falling edge of STROBE. A logical "1" written into a memory cell turns the corresponding crosspoint switch on and a logical "0" turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. A logical "1" on the RESET input will asynchronously return all memory locations to logical "0" turning off all crosspoint switches regardless of whether CS is high or low. Two voltage reference pins (V SS and V EE) are provided for the MT8806 to enable switching of negative analog signals. The range for digital signals is from V DD to V SS while the range for analog signals is from V DD to VEE. V SS and VEE pins can be tied together if a single voltage reference is needed.
MT8806
Address Decode
The five address inputs along with the STROBE and CS (Chip Select) inputs are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low and CS must go high while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch.
3-11
MT8806
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated.
Parameter 1 2 3 4 5 6 Supply Voltage Analog Input Voltage Digital Input Voltage Current on any I/O Pin Storage Temperature Package Power Dissipation PLASTIC DIP CERDIP Symbol VDD VSS VINA VIN I TS PD PD -65 Min -0.3 -0.3 -0.3 VSS-0.3 Max 15.0 VDD+0.3 VDD+0.3 VDD+0.3 15 +150 0.6 1.0 Units V V V V mA C W W
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated.
Characteristics 1 2 3 4 Operating Temperature Supply Voltage Analog Input Voltage Digital Input Voltage Sym TO VDD VSS VINA VIN Min -40 4.5 VEE VEE VSS Typ 1 0.4 5 2 3 4 5 6 Off-state Leakage Current (See G.9 in Appendix) Input Logic "0" level Input Logic "1" level Input Logic "1" level Input Leakage (digital pins) IOFF VIL VIH VIH ILEAK
2.0+VSS
Typ 25
Max 85 13.2 VDD-4.5 VDD VDD
Units C V V V V
Test Conditions
DC Electrical
1
Characteristics- Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated.
Sym IDD Min Max 100 1.5 15 500
0.8+VS
S
Characteristics Quiescent Supply Current
Units A mA mA nA V V V
Test Conditions All digital inputs at VIN=VSS or VDD All digital inputs at VIN=2.4 + VSS ; VSS =7.0V All digital inputs at VIN=3.4V IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 VSS =7.5V; VEE=0V VSS =6.5V; VEE=0V All digital inputs at VIN = VSS or VDD
1
3.3 0.1 10
A
DC Electrical Characteristics are over recommended temperature range. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics Sym 25C Typ 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) 2 Difference in on-state resistance between two switches (See G.4 in Appendix)
3-12
70C Typ Max 75 85 215
85C Typ Max 80 90 225
Units
Test Conditions
Max 65 75 185
RON
45 55 120

VSS=VEE=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2
RON
5
10
10
10
VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2
ISO-CMOS
MT8806
AC Electrical Characteristics - Crosspoint Performance - Voltages are with respect to VDD=5V, VSS=0V,
VEE=-7V, unless otherwise stated.
Characteristics 1 2 3 Switch I/O Capacitance Feedthrough Capacitance Frequency Response Channel "ON" 20LOG(VOUT/VXi)=-3dB Total Harmonic Distortion (See G.5, G.6 in Appendix) Feedthrough Channel "OFF" Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix).
Sym CS CF F3dB
Min
Typ 20 0.2 45
Max
Units pF pF MHz
Test Conditions f=1 MHz f=1 MHz Switch is "ON"; VINA = 2Vpp sinewave; RL = 1k See Appendix, Fig. A.3 Switch is "ON"; VINA = 2Vpp sinewave f= 1kHz; RL=1k All Switches "OFF"; VINA= 2Vpp sinewave; f= 1kHz; RL= 1k. See Appendix, Fig. A.4 VINA=2Vpp sinewave f= 10MHz; RL = 75. VINA=2Vpp sinewave f= 10kHz; RL = 600. VINA=2Vpp sinewave f= 10kHz; RL = 1k. VINA=2Vpp sinewave f= 1kHz; RL = 10k. Refer to Appendix, Fig. A.5 for test circuit. RL=1k; CL=50pF
4 5
THD FDT
0.01 -95
% dB
6
Xtalk
-45 -90 -85 -80
dB dB dB dB
7
Propagation delay through switch
tPS
30
ns
Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics - Control and I/O Timings- Voltages are with respect
VEE=-7V, unless otherwise stated.
to VDD=5V, VSS=0V,
Characteristics 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) Digital Input Capacitance Switching Frequency Setup Time DATA to STROBE Hold Time DATA to STROBE Setup Time Address to STROBE Hold Time Address to STROBE Setup Time CS to STROBE Hold Time CS to STROBE STROBE Pulse Width RESET Pulse Width STROBE to Switch Status Delay DATA to Switch Status Delay
Sym CXtalk
Min
Typ 30
Max
Units mVpp
Test Conditions VIN=3V squarewave; RIN=1k, RL=10k. See Appendix, Fig. A.6 f=1MHz RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, RL= 1k, 1k, CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF CL=50pF
2 3 4 5 6 7 8 9 10 11 12 13
CDI FO tDS tDH tAS tAH tCSS tCSH tSPW tRPW tS tD 10 10 10 10 10 10 20 40
10 20
pF MHz ns ns ns ns ns ns ns ns
40 50
100 100
ns ns
Q
14 RESET to Switch Status Delay tR 35 100 ns RL = Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Refer to Appendix, Fig. A.7 for test circuit.
Q Q Q Q Q Q Q Q Q Q Q
3-13
MT8806
ISO-CMOS
tCSS 50% CS
tCSH 50% tRPW 50% 50%
RESET
tSPW 50% tAS 50% 50%
STROBE
ADDRESS
50%
50% tAH
DATA
50% tDS ON tDH
50%
SWITCH* OFF tD tS tR tR
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AX0
0 0 0 0 0 0 0 0 1 1 0 0 1 1
AX1
0 0 0 0 0 0 0 0 0 0 1 1 1 1
AY0
0 1 0 1 0 1 0 1 0 1 0 1 0 1
AY1
0 0 1 1 0 0 1 1 0 1 0 1 0 1
AY2
0 0 0 0 1 1 1 1 0 1 0 1 0 1
Connection
X0-Y0 X0-Y1 X0-Y2 X0-Y3 X0-Y4 X0-Y5 X0-Y6 X0-Y7 X1-Y0 X1-Y7 X2-Y0 X2-Y7 X3-Y0 X3-Y7
Table 1. Address Decode Truth Table
3-14

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